2337 Digital Logic Design

2337 Digital Logic Design

Catalog Description: Boolean algebra, number systems and representations, analysis and design of combinational and sequential logic circuits, minimization, small and medium-scale integrated devices, programmable logic, and simulation of digital circuits.

Textbook: Digital Design: Principles and Practices by John F Wakerly, 4^thEdition.

Course Objectives:

Students will learn various numbering systems and their appropriate use in digital systems design.
Students will learn the basic concepts of Boolean algebra and how to manipulate Boolean equations.
Students will learn minimization techniques for designing efficient combinational and sequential logic circuits.
Students will be familiar with basic digital circuit building blocks (for example, decoders, multiplexers, shift registers) and be able to incorporate these fundamental logic circuits into larger, more complicated digital designs.
Students will learn the electrical characteristics of fundamental combinational and sequential circuits and understand the impact of these characteristics on digital designs.
Students will learn basic sequential circuit design methods and understand the use of flip-flops and latches.
Students will learn modern software tools for implementing and designing digital systems.
Students will be introduced to VHDL for designing and simulating digital circuits.

Syllabus - Spring Semester 2007

EGR 2337 Digital Logic Design
Week	Dates		Topics		Reading Assignment/Lab/Exam Schedule
1	Jan 8-12		Overview and Introduction Number Systems and Codes		Chapter 1 2.2-2.6
2	Jan 15 MLK Hol Jan 17-19		Number Systems and Codes		2.8-2.16 (Skip 2.7, 2.14 and 2.15.2-2.15.7) Lab Time - Number System Practice
3	Jan 22-26		Logic Gates, CMOS Digital Circuits CMOS Static and Dynamic Behavior		3.1-3.3 3.4-3.6 Lab 1 – TTL SSI Gates
4	Jan 29 – Feb 2		CMOS I/O Structures and Families Boolean Algebra Combinational Analysis and Synthesis		3.7-3.8 (Survey 3.9-3.10) 4.1 4.2-4.3.2 Lab 2 – Rock, Paper, Scissors
5	Feb 5-9		Combinational Analysis and Synthesis Karnaugh Maps		Exam 1 – Chapters 1-3 4.3.3-4.3.5 (Skip 4.3.6-4.4) Lab 3 – Ripple Adders
6	Feb 12-16		Introduction to VHDL		5.1 and 5.3 (Skip 5.2 and 5.4) Lab 4 –LED Decoder with VHDL
7	Feb 19-23		Combinational Logic Design Documentation Standards, Timing, PLDs, Decoders, Encoders, Three-State Devices, Multiplexers		6.1-6.7 (Skip sections on ABEL and Verilog) Lab 5 – Multiplexers and Time-Division Multiplexing
8	Feb 26 – Mar 2		Combinational Logic Design XOR and Parity Circuits, Comparators Combinational Mathematic Circuits		6.8-6.10 (Skip sections on ABEL and Verilog) Lab 6 – ALU Design
9	Mar 5-9		Sequential Logic Design Principles Latches, Flip-Flops and Registers		Exam 2 – Chapters 4-6 7.1-7.2 Lab 7 – Latches, Flip-Flops, and Registers
Mar 12-16		Spring Break
10	Mar 19-23		State Machine Analysis and Design		7.4-7.5 (Skip 7.4.5, 7.6) Lab Time – State Machine Practice
11	Mar 26-30		State Machine Analysis and Design		7.7, 7.8, 7.12 (Skip 7.9-7.11 and 7.13) Lab 8 – State Machine Design
12	Apr 2-4 Apr 6 Easter Hol		Sequential Circuit Design Practices, Latches and Flip-flops, Sequential PLDs Counters, and Shift Registers		8.1-8.5 No Lab
13	Apr 9 Easter Hol Apr 11-13		Synchronous Design Methodology, Impediments to Synchronous Design, Synchronizers and Metastability		8.7-8.9 (Skip 8.6) Lab 9 – Interacting State machines and CPLD Timing
14	Apr 16-20		Memory		9.1-9.4 Lab 10 – Memory
15	Apr 23-27		CPLDs and FPGAs		9.5-9.6 Lab TBD
16	Apr 30		CPLDS and FPGAs		Last day of class lectures
Final Exam		Tuesday, May. 8 9:00-11:00 AM		Final Exam

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